The present invention relates generally to an optical Partial Response Maximum Likelihood (PRML) read channel, and particularly to an apparatus and method for error calculations and ideal value estimation in an optical PRML read channel.
DVD, an acronym for Digital Video Disc or Digital Versatile Disc, is a relatively new type of Compact-Disc Read-Only-Memory (CD-ROM) with a minimum capacity of approximately 4.7 gigabytes. FIG. 1 illustrates in block diagram form apparatus for recording to and reading data from DVD 22. Recording Unit 20 takes digital data represented by the mk signal and records it on DVD 22. (The subscript xe2x80x9ckxe2x80x9d is used throughout to indicate generally a time-variant signal and the subscript xe2x80x9cknxe2x80x9d indicates the value of a time-variant signal at a time k+n.) Recording Unit 20 includes an Eight-to-Fourteen Modulator (EFM) 21. EFM 21 translates each block of 8 data bits represented by the mk signal into a block of 14 channel bits, selected for its specific bit pattern. To control the length of the pits on DVD 22, EFM 21 uses only those 14 bit sequences that include two, but less than ten, consecutive 0s. These constraints are referred to as (d=2, k=10) in DVD literature.
DVD player 24 includes Optical Pick-up Unit (OPU) 26, Automatic Gain Control (AGC) and Equalization Circuitry 28, Analog-to-Digital Converter (ADC) 34, Viterbi Decoder 46, and Clock 40. OPU 26 converts information read from DVD 22 into an analog RF signal on line 27. AGC and Equalization Circuitry 28 filters and limits the voltage magnitude of the EFM encoded RF signal on line 27, producing the analog zk signal on line 33. ADC 34 samples the EFM encoded analog signal on line 33 and produces a multi-bit digital, EFM encoded signal on line 35. A single sample of an EFM encoded signal is referred to herein as an EFM datum. Viterbi Decoder 36 analyzes several EFM datums and determines the most likely value represented by each EFM datum. Clock 40 generates a clock signal, CK, from the digital signal on line 35. The CK signal is used by AGC and Equalization Circuitry 28, ADC 34 and Viterbi Decoder 46.
Both Clock 40 and AGC and Equalization Circuitry 28 include Error Calculators 50, which generate error signals used to improve circuit performance. FIG. 2 illustrates prior art Error Calculator 50 in block diagram form. Error Calculator 50 receives the output signal from its associated circuit, the yk signal, from which an error signal, ek, is generated. A value of the yk signal at a time k is an EFM datum. Over several clock cycles the yk signal represents a sequence of EFM datums. Error Calculator 50 includes Quantizer 52 and Summer 54. Quantizer 52 determines the ideal value, yk{circumflex over ( )}, for the EFM datum currently represented by the yk signal. Quantizer 52 determines the ideal value, yk{circumflex over ( )}, using Relationship (1).
yk{circumflex over ( )}=q*round(yk/q); xe2x80x83xe2x80x83(1)
where q represents a quantization interval; and xe2x80x9croundxe2x80x9d represents a rounding function.
Summer 54 determines the error of the input signal, yk, by subtracting it from the corresponding ideal value. Thus, the error signal, ek, is given by Expression (2).
ek=yk{circumflex over ( )}xe2x88x92yk.xe2x80x83xe2x80x83(2)
Error signal estimation is adversely affected by baseline wandering of the zk signal (See FIG. 1). As used herein, baseline wandering refers to low frequency disturbances of a radio frequency signal. Baseline wandering of the zk signal leads to errors in the yk signal, which in turn leads to errors in the ideal value signal, the yk{circumflex over ( )} signal. These errors degrade the performance of the AGC and Equalization Circuitry 28 and Clock 40. Thus, a need exists for improved error signal calculation and ideal value estimation in Optical PRML read channels.
The apparatus of the present invention improves ideal value estimation for Eight-Fourteen Modulated (EFM) data, thus enabling improved error calculations in an Optical PRML Reach Channel. The apparatus of the present invention includes a peak detector and modification circuitry. The peak detector receives a first set of signals representing initial values of a sequence of EFM datums, each of which has an initial value that is a member of a first set of values including {xe2x88x92b, xe2x88x92a, c, a, b} where |b| greater than |a| greater than |c|. The peak detector analyzes a first subsequence of the sequence of EFM datums to determine whether a peak has occurred and, if so, asserts a modify signal. The modification circuitry responds to assertion of the modify signal by replacing the initial values of a second subsequence of the sequence EFM datums with revised values. The second subsequence of EFM datums follows the first subsequence of EFM datums and each revised value of the second subsequence has an absolute value that is a member of the first set of values.